Chip development costs incurred in technological development boom slowing down

"SoC design using CMOS technology have been fine to 65nm. This will result in skyrocketing costs of trial, and even research and development is also difficult. And the total chip development costs will reach 100 million U.S. dollars scale. Even put into these development costs, also can be difficult to find a cost-recovery purposes "(American Analog Devices high-speed signal processing business unit, product line director David Robertson).

"CMOS golden age" has ended?

"Nikkei Electronics" on June 25, 2007 organized a technical seminar, "Simulation Technology Forum 2007." At the seminar, analog circuit design the latest technological developments and technical personnel training related to a speech concern. In the area of analog circuit design, Analog Devices said David Robertson, CMOS process slowed the progress of miniaturization of CMOS analog circuit design technology. "In the 1990s can be called the 'CMOS golden age'. People are able to use the most cutting-edge CMOS technology, to conduct research and development of CMOS analog circuits. Thus, technology has developed rapidly. However, recently, into the 65nm technology era, the most cutting-edge technology has been very difficult for in trial use. University especially. In this case, technological developments may slow down "(Robertson).

Robertson believes that to overcome this problem, it is important that the cooperation between enterprises. Moreover, no reluctance to carry out single-chip-based (SoC), were most suitable for the use of analog and digital technology, then a different chip installed in a module (SiP, etc.), find this method is also very important.

In the technical staff training, were wild Institute of analog circuit simulation techniques were wild Takao on the front line of staff training were introduced. In the question time, one after another tells the audience of enterprise technology, training of personnel difficulties.

In the rest of the speech, Fujitsu Research Institute to work on the realization of a 0.8V pipelined AD converter delivered a speech on the development of the Tokyo Institute of Technology professor Song Zezhao for nano-CMOS era of analog circuit technology, National Semiconductor in Japan for mobile products with computing amplifier technology, the U.S. Texas Instruments (TexasInstruments) for portable battery-margin technology trends into account separately the report.